1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel multiple chip module (MCM) packaging configuration to simplify assembling and testing processes of MCM such that a lower production cost is achieved, and to simplify the procedures to repackage and utilize the know-good-die (KGD) after testing such that an effective method is provided to minimize the wastes of the known-good-dice.
2. Description of the Prior Art
There is a challenge faced by those applying the multiple chip module (MCM) technology to package multiple electronic chips into a single module. This challenge arises from the fact that a MCM module can function properly only if every chip assembled into this MCM package is individually a good die. Also, due to the accumulative effect, even a small percentage of reject rate for the individual chips generates an unacceptable loss to the MCM packages using these chips. For example, a 99% chip acceptance rate for the individual chips, when assembled into eight-chip modules (X8 modules) as dual in-line memory module (DIMM) or single-in-line-memory module (SIMM) packages, an 8% loss or rework rate is generated which is clearly unacceptable.
In order to reduce wastes of resources committed to packaging chips which are not good dice, burn-in tests of individual chips are performed to identify the known good dice (KGD) before a MCM packaging processes are carried out. However, the processes for burning-in each individual chip or chip-size package (CSP) are very expensive due to the requirements of special testing sockets, and large dedicated burn-in board. Furthermore, difficult handling techniques are required to test these individual chips. Due to these special and expensive requirements for qualifying an integrated circuit (IC) chip as a known good die (KGD), it generally costs more to test a chip than to test a package. For the same reasons, the price of a known good die is approximately five to seven times as that of a untested die. Even with the high cost of testing and a much higher price to use the KGD, due to the concern of accumulative losses when chips are assembled as multiple chip modules, there is no choice but to employ the KGDs.
In addition to the costs related to the requirement of using the known good dice, two level of substrates are employed in conventional multiple chip modules wherein known good dice are assembled. The first level of substrate is used for packaging individual chips. The multiple chip module substrate is a second level substrate which is used for mounting multiple chips. Additional costs are incurred in this two level substrate structure since it requires more material and processing. This two substrate structure further presents another disadvantage that the packages have a high profile. In order to enhance device miniaturization, more and more modern applications implemented with packaged electronic chips require a reduced thickness. Conventional MCM packages implemented with a two-level substrate structure have very limited usefulness in modern miniaturized devices when an electronic packages with a very small thickness are required.
Therefore, a need still exits in the art to provide an improved configuration and procedure for testing and packaging the multiple chip modules to reduce the cost of testing and to more conveniently and economically reuse the known good dice when a known good die is packaged with other failed chips into a multiple-chip-module.